1. Field of the Invention
The present invention relates to a spin-transfer torque magnetic random access memory (STTMRAM), and, more particularly, to an STTMRAM element having a free layer with a laminated structure of magnetic and non-magnetic layers.
2. Description of the Prior Art
Spin transfer torque magnetic random access memory (STTMRAM) is one of the next generations of non-volatile memory currently under development. In STTMRAM, writing magnetic bits is achieved by using a spin polarized current through the magnetic tunnel junction (MTJ), instead of using a magnetic field. The STTMRAM write current scales down with smaller MTJ size in future technology nodes. STTMRAM has significant advantages over magnetic-field-switched (toggle) MRAM, which has been recently commercialized. One of the main drawbacks associated with field switched MRAM is its more complex cell architecture, which utilizes bypass line and remote write lines in one transistor and one MTJ design. Additional drawback includes its high write current (currently in the order of milli Amps (mA)) and poor scalability, which is currently limited to about 65 nano meters (nm). In addition, the field required to switch the bit, i.e. the current required to write the bits, increases rapidly as the size of the MTJ elements shrinks. On the other hand, the STTMRAM, which utilizes the spin transfer torque (STT) writing technology by directly passing a current through the MTJ, overcomes these hurdles with much lower switching current (in the order of micro A). This results in a simpler cell architecture that can be as small as 6F2 (for single-bit cells) and reduced manufacturing cost, and more importantly, improved scalability.
The STTMRAM memory for high-density and high-speed memory applications requires substantial reduction of the intrinsic current density to switch the magnetization of the free layer while maintaining high thermal stability, which is required for long-term data retention. Low switching (write) current is required mainly for reducing the size of the select transistor of the memory cell, which is typically coupled in series with MTJ to achieve smaller memory cell size and thus the highest possible memory density. The program or write current for a given transistor is proportional to the channel width (in unit of F) of the transistor. Thus, an STTMRAM with lower switching current requires smaller transistor and hence smaller cell size. In addition, a smaller voltage-drop across MTJ is required during programming as it decreases the probability of tunneling barrier degradation and breakdown, ensuring better write endurance for the device. This is particularly important for STTMRAM, because both read and write currents are driven through MTJ cells.
Thus, there is a need for an STTMRAM with low intrinsic current and rapid switching and small cell size.